1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor device that supports a built-in self-test (BIST) operation.
2. Description of the Related Art
As semiconductor fabrication technology advances, the integration degree of semiconductor devices is increased and the possibility of the semiconductor devices malfunctioning also increases. Problems in the fabrication process of semiconductor devices may be figured out by analyzing the malfunctions of the semiconductor devices, and this problem tracking process is important.
Semiconductor devices are tested using external test equipment. However, as multi-semiconductor package technology, where a plurality of semiconductor devices are mounted on one package is introduced, the conventional way of testing semiconductor devices needs changing. Multi-semiconductor packages use a plurality of internal memories having wide data input/output (I/O) bandwidth for improved performance. It becomes inefficient to test the memories inside the multi-semiconductor package with conventional testing equipment, due to lack of channels on the test equipment, limitations in high-speed testing, and low accessibility to the internal memories.
To alleviate such issues, a method of including a built-in self-test (BIST) circuit inside the multi-semiconductor package is suggested. Since this method is advantageous in terms of high-speed testing over the conventional method, it has been developed and, nowadays, it is widely used as a method for testing internal memories of multi-semiconductor packages.